FLEXCASE E 2.1 SPI Communication CLOCK Problem

[xuanlang]

#18434

Hi Audesse Team,

I am working on communication between the FLEXCASE E 2.1 and the QCA chip.
I am trying to control ChipSelect manually for this application but encountered some issues.
when sending the SPI frame with configuration SpiShiftClockIdleLevel= HIGH, there is always a small dropdown jitter before the actual clock (see SpiShiftClockIdleLevel_HIGH_Custom_CS.png)
This is causing the spi to read the wrong first byte (should be 0xDA instead of 0xED)
 
But if SpiShiftClockIdleLevel= LOW, there is no such problem (see SpiShiftClockIdleLevel_LOW_Custom_CS.png)

I can get away with this if I let SPI driver to control the Chipselect (CS_VIA_PERIPHRAL_ENGINE, see SpiShiftClockIdleLevel_HIGH_Default_CS.png), but my application will require manual control of chip select)

Do you encounter something similar, and do you know if this is related to hardware or software configuration? Any insight will be helpful.

Thanks,
Xuanlang

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[xuanlang]

#18438

My Tool Chain is MATLAB2022B + NXP S32k3 MBDT 1.3

[AmirF]

#18452

Hi Xuanlang,

As you mentioned, since the QCA chip on the PLC module uses SPI mode 3, SpiShiftClockIdleLevel= HIGH is the correct configuration. You can also modify the CPHA using SpiSamplePoint parameter in the config tool.

I haven’t had this issue before, but I can think of a suggestion and a workaround for your application.
1. Software is the issue and it might indicate that you are using a different SPI mode. Please make sure you are running it in SPI mode 3.
2. You can use this workaround if the first suggestion doesn’t work. You can let the software drive the CS pin, but give it a dummy pin(a pin that is not connected or used, like PTF19 for FCE2.1) to drive it. You will still be able to drive the actual CS pin manually. Or alternatively, just define the CS pin as GPIO in the pinout tab and don’t define the SPICS.

Sincerely,

Amir

[xuanlang]

#18475

Hi Amir,

Currently the result is tested with defining the CS pin as GPIO and our software control the CS pin manually with DIO API (custom CS)

I am setting SpiShiftClockIdleLevel= HIGH (CPOL) and SpiDataShiftEdge = LEADING (CPHA) for mode3. I did not find the SpiSamplePoint config parameter in the config tool (s32ConfigTools2022R1.6)

The clock jitter only happened when I used SpiShiftClockIdleLevel= HIGH (CPOL) and across different hardware.

Do you have an example spi file that use Mode3 but does not have the clock jitter?

Thanks,
Xuanlang

[AmirF]

#18478

Hi Xuanlang,

1. For MBDT1.3 you can find the SpiSamplePoint in the following path in the config tool:
Peripherals>Spi>SpiGeneral>SpiPhyUnit>SpiSamplePoint.

2. If changing the SpiSamplePoint didn’t help, please use the workaround. In this approach, you set up the SPI such that there is no CLK jitter, let the Spi Phy Unit control a dummy CS(like PTF19, as mentioned before), and control the actual CS pin as GPIO in the code. This way, you get to control the CS manually, and there will be no clock jitter.

Sincerely,
Amir

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